555 search results - page 11 / 111 » Efficiently Implementing Episodic Memory |
IS
2008
13 years 9 months ago
2008
Implementations that load XML documents and give access to them via, e.g., the DOM, suffer from huge memory demands: the space needed to load an XML document is usually many times...
ISCA
2008
IEEE
13 years 9 months ago
2008
IEEE
Current hardware transactional memory systems seek to simplify parallel programming, but assume that large transactions are rare, so it is acceptable to penalize their performance...
ACNS
2006
Springer
14 years 1 months ago
2006
Springer
CPU bound client puzzles have been suggested as a defense mechanism against connection depletion attacks. However, the wide disparity in CPU speeds prevents such puzzles from being...
GLOBECOM
2008
IEEE
13 years 10 months ago
2008
IEEE
As the network line rates reach 40 Gbps today and 100 Gbps in the near future, performing deep packet inspection (DPI) in the Network Intrusion Detection and Prevention Systems (NI...
MICRO
1997
IEEE
14 years 2 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...