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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
14 years 4 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
IEEEPACT
1998
IEEE
14 years 2 months ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
PPOPP
2010
ACM
14 years 7 months ago
Scheduling support for transactional memory contention management
Transactional Memory (TM) is considered as one of the most promising paradigms for developing concurrent applications. TM has been shown to scale well on multiple cores when the d...
Walther Maldonado, Patrick Marlier, Pascal Felber,...
CCECE
2009
IEEE
14 years 4 months ago
Design and implementation of a low-power workstation
A workstation requires a low-power design similar to a typical PC. In this paper we propose several strategies to reduce the power consumption of a workstation. First, we must com...
Ying-Wen Bai, Chun-Yang Tsai
HICSS
1997
IEEE
98views Biometrics» more  HICSS 1997»
14 years 1 months ago
Recovery and Page Coherency for a Scalable Multicomputer Object Store
This paper presents scalable algorithms for recovery and page coherency in multicomputer object stores. Recovery and coherency are central to object store engineering and distribu...
Stephen M. Blackburn, Robin B. Stanton, Stephan J....