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» Efficiently Implementing Episodic Memory
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EH
2004
IEEE
117views Hardware» more  EH 2004»
14 years 12 days ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ICASSP
2010
IEEE
13 years 8 months ago
Buffer management for multi-application image processing on multi-core platforms: Analysis and case study
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...
Dong-Ik Ko, Nara Won, Shuvra S. Bhattacharyya
TPDS
2008
97views more  TPDS 2008»
13 years 8 months ago
Solving Systems of Linear Equations on the CELL Processor Using Cholesky Factorization
: The STI CELL processor introduces pioneering solutions in processor architecture. At the same time it presents new challenges for the development of numerical algorithms. One is ...
Jakub Kurzak, Alfredo Buttari, Jack Dongarra
IJCV
2002
129views more  IJCV 2002»
13 years 8 months ago
A Hierarchical Symmetric Stereo Algorithm Using Dynamic Programming
In this paper, a new hierarchical stereo algorithm is presented. The algorithm matches individual pixels in corresponding scanlines by minimizing a cost function. Several cost fun...
G. Van Meerbergen, Maarten Vergauwen, Marc Pollefe...
TCOM
2010
133views more  TCOM 2010»
13 years 3 months ago
Low-complexity decoding for non-binary LDPC codes in high order fields
In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts...
Adrian Voicila, David Declercq, François Ve...