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CHINAF
2006
110views more  CHINAF 2006»
15 years 4 months ago
Time-domain analysis methodology for large-scale RLC circuits and its applications
: With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical d...
Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong ...


views
56 years 3 months ago
GLVLSI
2009
IEEE
159views VLSI» more  GLVLSI 2009»
15 years 11 months ago
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
This paper discusses the impact of migrating from 2-D to 3-D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3-...
Renshen Wang, Chung-Kuan Cheng
DAC
2005
ACM
15 years 6 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
ICCD
2004
IEEE
172views Hardware» more  ICCD 2004»
16 years 1 months ago
A Signal Integrity Test Bed for PCB Buses
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
Jihong Ren, Mark R. Greenstreet