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RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
14 years 23 days ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
RTSS
2003
IEEE
14 years 23 days ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
CCS
2008
ACM
13 years 9 months ago
CMV: automatic verification of complete mediation for java virtual machines
Runtime monitoring systems play an important role in system security, and verification efforts that ensure that these systems satisfy certain desirable security properties are gro...
A. Prasad Sistla, V. N. Venkatakrishnan, Michelle ...
USENIX
2003
13 years 8 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
CODES
2008
IEEE
14 years 2 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava