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ARC
2007
Springer
150views Hardware» more  ARC 2007»
14 years 1 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
CGO
2004
IEEE
14 years 1 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
ICFP
2010
ACM
13 years 11 months ago
Scrapping your inefficient engine: using partial evaluation to improve domain-specific language implementation
Partial evaluation aims to improve the efficiency of a program by specialising it with respect to some known inputs. In this paper, we show that partial evaluation can be an effec...
Edwin Brady, Kevin Hammond
LCTRTS
2007
Springer
14 years 4 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
ESTIMEDIA
2007
Springer
14 years 4 months ago
Run-time Task Overlapping on Multiprocessor Platforms
Today’s embedded applications often consist of multiple concurrent tasks. These tasks are decomposed into subtasks which are in turn assigned and scheduled on multiple different...
Zhe Ma, Daniele Paolo Scarpazza, Francky Catthoor