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CAMP
2005
IEEE
14 years 19 days ago
Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
Domenico Barretta, Gianluca Palermo, Mariagiovanna...
ICCD
2004
IEEE
123views Hardware» more  ICCD 2004»
14 years 7 months ago
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures
The work presents a modeling and analysis framework for heterogeneous industrial networks architectures which is based on a tight integration of a network simulator with embedded ...
Franco Fummi, Stefano Martini, Marco Monguzzi, Gio...
CODES
2002
IEEE
14 years 3 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
CGO
2008
IEEE
14 years 5 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
14 years 4 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...