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CODES
2006
IEEE
14 years 3 months ago
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
Dong-Ik Ko, Shuvra S. Bhattacharyya
ESTIMEDIA
2004
Springer
14 years 2 months ago
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
Tien-Wei Hsieh, Youn-Long Lin
DSN
2003
IEEE
14 years 2 months ago
Integrating Recovery Strategies into a Primary Substation Automation System
The DepAuDE architecture provides middleware to integrate fault tolerance support into distributed embedded automation applications. It allows error recovery to be expressed in te...
Geert Deconinck, Vincenzo De Florio, Ronnie Belman...
WSTFEUS
2003
IEEE
14 years 2 months ago
SCA-based Component Framework for Software Defined Radio
SCA (Software Communication Architecture), which has been adopted as a SDR (Software Defined Radio) Forum standard, provides a framework that successfully exploits common design p...
Saehwa Kim, Jamison Masse, Seongsoo Hong, Naehyuck...
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
14 years 2 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock