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DFT
2002
IEEE
128views VLSI» more  DFT 2002»
14 years 27 days ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
TCAD
2008
183views more  TCAD 2008»
13 years 7 months ago
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
Abstract--For modern embedded systems in the realm of highthroughput multimedia, imaging, and signal processing, the complexity of embedded applications has reached a point where t...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
IH
2005
Springer
14 years 1 months ago
Dither Modulation Watermarking of Dynamic Memory Traces
We describe a dynamic software watermark embedded in the memory trace of an executing Java program. Our approach is a generalisation of the spread–transform watermarking techniqu...
Alan J. Larkin, Félix Balado, Neil J. Hurle...
SAC
2008
ACM
13 years 7 months ago
A hybrid software-based self-testing methodology for embedded processor
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
14 years 26 days ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin