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JSA
2010
158views more  JSA 2010»
13 years 2 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
CASES
2006
ACM
14 years 1 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
ASPDAC
2006
ACM
131views Hardware» more  ASPDAC 2006»
14 years 1 months ago
POSIX modeling in SystemC
- Early estimation of the execution time of Real-Time embedded SW is an essential task in complex, HW/SW embedded system design. Application SW execution time estimation requires t...
Hector Posadas, Jesús Ádamez, Pablo ...
IPPS
2007
IEEE
14 years 1 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
ISCAS
2007
IEEE
103views Hardware» more  ISCAS 2007»
14 years 1 months ago
A Low-cost and High-performance SoC Design for OMA DRM2 Applications
A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several...
Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao