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DATE
2004
IEEE
131views Hardware» more  DATE 2004»
15 years 6 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
CSREAESA
2009
15 years 3 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
GECCO
2005
Springer
155views Optimization» more  GECCO 2005»
15 years 8 months ago
Mission planning for joint suppression of enemy air defenses using a genetic algorithm
In this paper we present a genetic algorithm applied to the problem of mission planning for Joint Suppression of Enemy Air Defenses (JSEAD) in support of air strike operations. Th...
Jeffrey P. Ridder, Jason C. HandUber
IJIT
2004
15 years 3 months ago
"Intuition" Operator: Providing Genomes with Reason
In this contribution, the use of a new genetic operator is proposed. The main advantage of using this operator is that it is able to assist the evolution procedure to converge fast...
Grigorios N. Beligiannis, Georgios A. Tsirogiannis...
112
Voted
TCAD
2002
110views more  TCAD 2002»
15 years 2 months ago
A constructive genetic algorithm for gate matrix layout problems
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
Alexandre César Muniz de Oliveira, Luiz Ant...