Sciweavers

65 search results - page 11 / 13
» Embedding path designs in 4-cycle systems
Sort
View
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
14 years 1 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
FCCM
2007
IEEE
108views VLSI» more  FCCM 2007»
14 years 1 months ago
Configurable Transactional Memory
Programming efficiency of heterogeneous concurrent systems is limited by the use of lock-based synchronization mechanisms. Transactional memories can greatly improve the programmi...
Christoforos Kachris, Chidamber Kulkarni
IJHPCA
2008
75views more  IJHPCA 2008»
13 years 7 months ago
Towards Ultra-High Resolution Models of Climate and Weather
We present a speculative extrapolation of the performance aspects of an atmospheric general circulation model to ultra-high resolution and describe alternative technological paths...
Michael F. Wehner, Leonid Oliker, John Shalf
CASES
2009
ACM
14 years 2 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
GD
2005
Springer
14 years 1 months ago
A Mixed-Integer Program for Drawing High-Quality Metro Maps
In this paper we investigate the problem of drawing metro maps which is defined as follows. Given a planar graph G of maximum degree 8 with its embedding and vertex locations (e.g...
Martin Nöllenburg, Alexander Wolff