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FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
15 years 8 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
VLDB
2007
ACM
174views Database» more  VLDB 2007»
16 years 4 months ago
An adaptive and dynamic dimensionality reduction method for high-dimensional indexing
Abstract The notorious "dimensionality curse" is a wellknown phenomenon for any multi-dimensional indexes attempting to scale up to high dimensions. One well-known approa...
Heng Tao Shen, Xiaofang Zhou, Aoying Zhou
CASES
2006
ACM
15 years 10 months ago
A case study of multi-threading in the embedded space
The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net proces...
Greg Hoover, Forrest Brewer, Timothy Sherwood
HPCA
2002
IEEE
16 years 4 months ago
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters
Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although c...
Peter Jamieson, Angelos Bilas
CLUSTER
2010
IEEE
14 years 8 months ago
Middleware support for many-task computing
Many-task computing aims to bridge the gap between two computing paradigms, high throughput computing and high performance computing. Many-task computing denotes highperformance co...
Ioan Raicu, Ian T. Foster, Mike Wilde, Zhao Zhang,...