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TCAD
2008
92views more  TCAD 2008»
13 years 8 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
MICRO
2007
IEEE
108views Hardware» more  MICRO 2007»
14 years 3 months ago
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...
CODES
2006
IEEE
14 years 3 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
HICSS
2006
IEEE
188views Biometrics» more  HICSS 2006»
14 years 3 months ago
Scalable Online Discussions as Listening Technology
This paper presents a novel online discussion environment that efficiently supports listening processes inspired by more collaborative management practices. This participative man...
Baldo Faieta, Bernardo A. Huberman, Paul Verhaeghe
FPGA
2009
ACM
482views FPGA» more  FPGA 2009»
14 years 1 months ago
A 17ps time-to-digital converter implemented in 65nm FPGA technology
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
Claudio Favi, Edoardo Charbon