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» Encoding Algorithms for Logic Synthesis
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126
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KBSE
2005
IEEE
15 years 7 months ago
Learning to verify branching time properties
We present a new model checking algorithm for verifying computation tree logic (CTL) properties. Our technique is based on using language inference to learn the fixpoints necessar...
Abhay Vardhan, Mahesh Viswanathan
148
Voted
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 6 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
GECCO
2008
Springer
175views Optimization» more  GECCO 2008»
15 years 3 months ago
Using differential evolution for symbolic regression and numerical constant creation
One problem that has plagued Genetic Programming (GP) and its derivatives is numerical constant creation. Given a mathematical formula expressed as a tree structure, the leaf node...
Brian M. Cerny, Peter C. Nelson, Chi Zhou
VTS
2007
IEEE
143views Hardware» more  VTS 2007»
15 years 8 months ago
RTL Test Point Insertion to Reduce Delay Test Volume
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
Kedarnath J. Balakrishnan, Lei Fang
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 8 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte