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166
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ERSA
2009
147views Hardware» more  ERSA 2009»
15 years 18 days ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
114
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CVPR
2000
IEEE
16 years 4 months ago
Robust and Efficient Skeletal Graphs
There has recently been significant interest in using repions based on abstractions of Blum's skeleton into a graph, for qualitative shape matching. The application of these ...
Pavel Dimitrov, Carlos Phillips, Kaleem Siddiqi
136
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HIPEAC
2009
Springer
15 years 6 months ago
Deriving Efficient Data Movement from Decoupled Access/Execute Specifications
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...
Lee W. Howes, Anton Lokhmotov, Alastair F. Donalds...
136
Voted
IJNSEC
2010
247views more  IJNSEC 2010»
14 years 9 months ago
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and imp...
Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail
111
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DAC
2006
ACM
16 years 3 months ago
Efficient SAT-based Boolean matching for FPGA technology mapping
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler...