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TCOS
2010
13 years 2 months ago
Green Secure Processors: Towards Power-Efficient Secure Processor Design
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the softwar...
Siddhartha Chhabra, Yan Solihin
TPDS
2002
105views more  TPDS 2002»
13 years 7 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
FPGA
1995
ACM
142views FPGA» more  FPGA 1995»
13 years 11 months ago
The Design of RPM: An FPGA-based Multiprocessor Emulator
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improveme...
Koray Öner, Luiz André Barroso, Sasan ...
DNA
2006
Springer
130views Bioinformatics» more  DNA 2006»
13 years 9 months ago
Displacement Whiplash PCR: Optimized Architecture and Experimental Validation
Whiplash PCR-based methods of biomolecular computation (BMC), while highly-versatile in principle, are well-known to suffer from a simple but serious form of self-poisoning known a...
John A. Rose, Ken Komiya, Satsuki Yaegashi, Masami...
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
13 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...