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DATE
2000
IEEE
110views Hardware» more  DATE 2000»
14 years 1 months ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann
POPL
2010
ACM
14 years 3 months ago
Lightweight asynchrony using parasitic threads
Message-passing is an attractive thread coordination mechanism because it cleanly delineates points in an execution when threads communicate, and unifies synchronization and comm...
K. C. Sivaramakrishnan, Lukasz Ziarek, Raghavendra...
ICC
2009
IEEE
109views Communications» more  ICC 2009»
14 years 3 months ago
Carrier-Sense ARQ: Squeezing Out Bluetooth Performance While Preserving Standard Compliancy
—In this paper, we propose a simple and standard compliant retransmission mechanism, called Carrier–Sense Automatic Repeat reQuest (CS–ARQ), which aims at improving system pe...
Andrea Zanella
INFOCOM
2002
IEEE
14 years 1 months ago
Ultrafast Photonic Label Switch for Asynchronous Packets of Variable Length
- This paper describes new optical switching architectures supporting asynchronous variable-length packets. Output line contention is resolved by optical delay line buffers. By int...
Masayuki Murata, Ken-ichi Kitayama
INFOCOM
2008
IEEE
14 years 3 months ago
Capacity of Asynchronous Random-Access Scheduling in Wireless Networks
Abstract—We study the throughput capacity of wireless networks which employ (asynchronous) random-access scheduling as opposed to deterministic scheduling. The central question w...
Deepti Chafekar, Dave Levin, V. S. Anil Kumar, Mad...