Sciweavers

    114 search results - page 5 / 23
    » Energy-efficient FPGA interconnect design
    Sort
    View
    75
    Voted
    DAC
    2000
    ACM
    90views Computer Architecture» more  DAC 2000»
    Interconnect testing in cluster-based FPGA architectures
    16 years 4 months ago
    Interconnect testing in cluster-based FPGA architectures
    Download  testlab.ics.uci.edu
    Ian G. Harris, Russell Tessier
    claim paper
    Read More »
    112
    Voted
    FPGA
    2004
    ACM
    147views FPGA» more  FPGA 2004»
    The SFRA: a corner-turn FPGA architecture
    15 years 9 months ago
    The SFRA: a corner-turn FPGA architecture
    Download  www.icsi.berkeley.edu
    FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
    Nicholas Weaver, John R. Hauser, John Wawrzynek
    claim paper
    Read More »
    112
    Voted
    ASPDAC
    2005
    ACM
    89views Hardware» more  ASPDAC 2005»
    Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
    15 years 5 months ago
    Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
    Download  www.ee.ucla.edu
    Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
    Yan Lin, Fei Li, Lei He
    claim paper
    Read More »
    127
    Voted
    GLVLSI
    2008
    IEEE
    197views VLSI» more  GLVLSI 2008»
    Efficient tree topology for FPGA interconnect network
    15 years 3 months ago
    Efficient tree topology for FPGA interconnect network
    Download  www-asim.lip6.fr
    This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
    Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
    claim paper
    Read More »
    132
    Voted
    DAC
    2003
    ACM
    157views Computer Architecture» more  DAC 2003»
    Low-power design methodology for an on-chip bus with adaptive bandwidth capability
    15 years 9 months ago
    Low-power design methodology for an on-chip bus with adaptive bandwidth capability
    Download  www.cs.york.ac.uk
    This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
    Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    i2PDF i2Img i2Text i2OCR i2Symbol i2Type i2Speak i2Style i2Arabic i2Bopomo Latex Equation Editor
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2026, USA.