This paper deals with general nested loops and proposes a novel scheduling methodology for reducing the communication cost of parallel programs. General loops contain complex loop...
Florina M. Ciorba, Theodore Andronikos, Ioannis Dr...
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Abstract. This paper presents a new approach to model and test hierarchical Graphical User Interfaces (GUIs). We exploit the structure of Hierarchical Finite State Machines (HFSMs)...
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
Todd S. Sproull, Gordon J. Brebner, Christopher E....
Many of today’s software applications require a high-level of security, defined by a detailed policy and attained via mechanisms such as role-based access control (RBAC), mandat...
Jaime A. Pavlich-Mariscal, Laurent Michel, Steven ...