146 search results - page 1 / 30 » Enhanced clustered voltage scaling for low power |
GLVLSI
2002
IEEE
14 years 12 days ago
2002
IEEE
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RTAS
2000
IEEE
13 years 11 months ago
2000
IEEE
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power di...
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...