This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
Modern combinational equivalence checking (CEC) engines are complicated programs which are difficult to verify. In this paper we show how a modern CEC engine can be modified to pr...
Satrajit Chatterjee, Alan Mishchenko, Robert K. Br...
This paper presents a verification technique which is specifically targeted to formally comparing large combinational circuits with some structural similarities. The approach co...
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...