122 search results - page 6 / 25 » Error tolerant associative memory |
122
Voted
SC
2009
ACM
15 years 10 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
127
Voted
IOLTS
2008
IEEE
15 years 10 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
131
Voted
ISLPED
2006
ACM
15 years 9 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
157
Voted
EMSOFT
2009
Springer
15 years 10 months ago
2009
Springer
While NAND flash memories have rapidly increased in both capacity and performance and are increasingly used as a storage device in many embedded systems, their reliability has de...
112
Voted
ISCA
2009
IEEE
15 years 10 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...