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» Estimating design time for system circuits
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ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
15 years 11 months ago
Silicon neurons that phase-lock
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
J. H. Wittig Jr., Kwabena Boahen
RTAS
2008
IEEE
16 years 3 days ago
Schedulability Analysis of MSC-based System Models
Message Sequence Charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimati...
Lei Ju, Abhik Roychoudhury, Samarjit Chakraborty
ICDE
2010
IEEE
292views Database» more  ICDE 2010»
16 years 5 months ago
Exploring Power-Performance Tradeoffs in Database Systems
With the total energy consumption of computing systems increasing in a steep rate, much attention has been paid to the design of energy-efficient computing systems and applications...
Zichen Xu, Yi-Cheng Tu, Xiaorui Wang
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
15 years 10 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
LCPC
2001
Springer
15 years 10 months ago
Bridging the Gap between Compilation and Synthesis in the DEFACTO System
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoun...