72 search results - page 9 / 15 » Estimation and optimization of reliability of noisy digital ... |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Efficient system-level design is increasingly relying on hierarchical design-space exploration, as well as compositional methods, to shorten time-to-market, leverage design re-use...
DSN
2005
IEEE
14 years 1 months ago
2005
IEEE
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
ICCV
1998
IEEE
13 years 12 months ago
1998
IEEE
We areinterestedin descriptionsof 3-D data sets,as obtained from stereoor a 3-D digitizer. We thereforeconsideras inputa sparsesetof points, possibly associated with certain orien...
TCAD
2008
13 years 7 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...