Sciweavers

71 search results - page 14 / 15
» Evaluating Block-level Optimization Through the IO Path
Sort
View
119
Voted
PPPJ
2009
ACM
15 years 10 months ago
Phase detection using trace compilation
Dynamic compilers can optimize application code specifically for observed code behavior. Such behavior does not have to be stable across the entire program execution to be beneļ¬...
Christian Wimmer, Marcelo Silva Cintra, Michael Be...
160
Voted
ACMSE
2004
ACM
15 years 9 months ago
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
Swathi Tanjore Gurumani, Aleksandar Milenkovic
ESA
2006
Springer
140views Algorithms» more  ESA 2006»
15 years 7 months ago
Latency Constrained Aggregation in Sensor Networks
A sensor network consists of sensing devices which may exchange data through wireless communication. A particular feature of sensor networks is that they are highly energy constrai...
Luca Becchetti, Peter Korteweg, Alberto Marchetti-...
141
Voted
IPPS
2005
IEEE
15 years 9 months ago
Reducing Power with Performance Constraints for Parallel Sparse Applications
Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational wor...
Guangyu Chen, Konrad Malkowski, Mahmut T. Kandemir...
139
Voted
TCAD
2010
124views more  TCAD 2010»
14 years 10 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas