501 search results - page 21 / 101 » Evaluating CMPs and Their Memory Architecture |
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
Multiprocessor memory reference traces provide a wealth of information on the behavior of parallel programs. We have used this information to explore the relationship between kern...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
TC
2010
13 years 2 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...