501 search results - page 35 / 101 » Evaluating CMPs and Their Memory Architecture |
ACSAC
2008
IEEE
14 years 2 months ago
2008
IEEE
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
ICS
2010
Tsinghua U.
13 years 10 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
ASPLOS
1998
ACM
13 years 12 months ago
1998
ACM
Several application and technology trends indicate that it might be both pro table and feasible to move computation closer to the data that it processes. In this paper, we evaluat...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
SIGARCH
2008
13 years 7 months ago
2008
This paper presents a parallelization framework for emerging applications on the future chip multiprocessors (CMPs). With the continuing prevalence of CMP and the number of on-die...