501 search results - page 41 / 101 » Evaluating CMPs and Their Memory Architecture |
HPCA
1997
IEEE
13 years 12 months ago
1997
IEEE
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
WOSP
2004
ACM
14 years 1 months ago
2004
ACM
The simulated evaluation of memory management policies relies on reference traces—logs of memory operations performed by running processes. No existing approach to reference tra...
IISWC
2008
IEEE
14 years 2 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...