501 search results - page 47 / 101 » Evaluating CMPs and Their Memory Architecture |
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
— We consider memory subsystem optimizations for improving the performance of sparse scientific computation while reducing the power consumed by the CPU and memory. We first co...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
Abstract. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memor...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...