501 search results - page 52 / 101 » Evaluating CMPs and Their Memory Architecture |
ASPLOS
2010
ACM
14 years 16 days ago
2010
ACM
Heterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existin...
TPDS
2002
13 years 7 months ago
2002
Many large scale applications have significant I/O requirements as well as computational and memory requirements. Unfortunately, the limited number of I/O nodes provided in a typic...
UAI
2001
13 years 9 months ago
2001
In this paper we present three different architectures for the evaluation of influence diagrams: HUGIN, Shafer-Shenoy (S-S), and Lazy Propagation (LP). HUGIN and LP are two new ar...
ICDE
2006
IEEE
14 years 9 months ago
2006
IEEE
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
NOCS
2007
IEEE
14 years 2 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...