501 search results - page 57 / 101 » Evaluating CMPs and Their Memory Architecture |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
ICPP
1997
IEEE
13 years 12 months ago
1997
IEEE
Most of recent research on distributed shared memory (DSM)systems have focused on either careful design of node controllersor cache coherenceprotocols. Whileevaluating these desig...
HIPC
1999
Springer
13 years 12 months ago
1999
Springer
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
CF
2010
ACM
14 years 24 days ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
RTAS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Dynamic RAM (DRAM) has been the best technology for main memory for over thirty years. In embedded space applications, radiation hardened DRAM is needed because gamma ray...