Sciweavers

501 search results - page 77 / 101
» Evaluating CMPs and Their Memory Architecture
Sort
View
SIGMETRICS
1990
ACM
129views Hardware» more  SIGMETRICS 1990»
13 years 11 months ago
An Analytical Model of Multistage Interconnection Networks
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
Darryl L. Willick, Derek L. Eager
EUROPAR
2007
Springer
13 years 9 months ago
Nested Parallelism in the OMPi OpenMP/C Compiler
This paper presents a new version of the OMPi OpenMP C compiler, enhanced by lightweight runtime support based on user-level multithreading. A large number of threads can be spawne...
Panagiotis E. Hadjidoukas, Vassilios V. Dimakopoul...
CADUI
2004
13 years 9 months ago
A Lightweight Experiment Management System for Handheld Computers
: This paper describes a system that helps HCI practitioners and researchers manage and conduct experiments involving context-sensitive handheld applications, particularly related ...
Philip D. Gray, Joy Goodman, James Macleod
PROCEDIA
2010
148views more  PROCEDIA 2010»
13 years 2 months ago
SysCellC: a data-flow programming model on multi-GPU
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...
Dominique Houzet, Sylvain Huet, Anis Rahman
HPCA
2006
IEEE
14 years 8 months ago
ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers
The increasing demand for reliable computers has led to proposals for hardware-assisted rollback of memory state. Such approach promises major reductions in Mean Time To Repair (M...
Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo...