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SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
14 years 3 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
GECCO
2007
Springer
268views Optimization» more  GECCO 2007»
14 years 4 months ago
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
Joachim Becker, Stanis Trendelenburg, Fabian Henri...
CCGRID
2009
IEEE
14 years 4 months ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
CASES
2008
ACM
14 years 1 days ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
PC
2010
177views Management» more  PC 2010»
13 years 8 months ago
Parallel graph component labelling with GPUs and CUDA
Graph component labelling, which is a subset of the general graph colouring problem, is a computationally expensive operation that is of importance in many applications and simula...
Kenneth A. Hawick, Arno Leist, Daniel P. Playne