Sciweavers

1304 search results - page 115 / 261
» Evaluating Hardware Compilation Techniques
Sort
View
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 9 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
ISCA
2010
IEEE
405views Hardware» more  ISCA 2010»
15 years 9 months ago
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
Recent advances in computing have led to an explosion in the amount of data being generated. Processing the ever-growing data in a timely manner has made throughput computing an i...
Victor W. Lee, Changkyu Kim, Jatin Chhugani, Micha...
CMG
2003
15 years 6 months ago
{Performance Modeling and Evaluation of Large-Scale J2EE Applications
The queueing Petri net (QPN) paradigm provides a number of benefits over conventional modeling paradigms such as queueing networks and generalized stochastic Petri nets. Using qu...
Samuel Kounev, Alejandro P. Buchmann
ICDE
2005
IEEE
121views Database» more  ICDE 2005»
16 years 6 months ago
Full-fledged Algebraic XPath Processing in Natix
We present the first complete translation of XPath into an algebra, paving the way for a comprehensive, state-of-theart XPath (and later on, XQuery) compiler based on algebraic op...
Matthias Brantner, Sven Helmer, Carl-Christian Kan...
CC
2002
Springer
131views System Software» more  CC 2002»
15 years 4 months ago
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
Andrea G. M. Cilio, Henk Corporaal