Sciweavers

1304 search results - page 117 / 261
» Evaluating Hardware Compilation Techniques
Sort
View
ECRTS
2000
IEEE
15 years 9 months ago
Towards validated real-time software
We present a tool for the design and validation of embedded real-time applications. The tool integrates two approaches, the use of the synchronous programming language ESTEREL for...
Valérie Bertin, Michel Poize, Jacques Pulou...
LCPC
1999
Springer
15 years 9 months ago
Instruction Scheduling in the Presence of Java's Runtime Exceptions
One of the challenges present to a Java compiler is Java’s frequent use of runtime exceptions. These exceptions affect performance directly by requiring explicit checks, as wel...
Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, B...
ISPASS
2007
IEEE
15 years 11 months ago
Cross Binary Simulation Points
Architectures are usually compared by running the same workload on each architecture and comparing performance. When a single compiled binary of a program is executed on many diff...
Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jal...
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
15 years 8 months ago
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip
Abstract-- Multiprocessor designs have become popular in embedded domains for achieving the power and performance requirements. In this paper, we present principles and techniques ...
Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
FDL
2003
IEEE
15 years 10 months ago
Object-Oriented ASIP Design and Synthesis
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft