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» Evaluating Hardware Compilation Techniques
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OOPSLA
2010
Springer
13 years 6 months ago
From OO to FPGA: fitting round objects into square hardware?
Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energyintensive operations in order to reduce overall energy consumption and i...
Stephen Kou, Jens Palsberg
IEEEPACT
2006
IEEE
14 years 1 months ago
Compiling for stream processing
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
Abhishek Das, William J. Dally, Peter R. Mattson
ISHPC
2000
Springer
13 years 11 months ago
Implementation and Evaluation of OpenMP for Hitachi SR8000
This paper describes the implementation and evaluation of the OpenMP compiler designed for the Hitachi SR8000 Super Technical Server. The compiler performs parallelization for the ...
Yasunori Nishitani, Kiyoshi Negishi, Hiroshi Ohta,...
IPPS
2003
IEEE
14 years 29 days ago
Performance Monitoring and Evaluation of a UPC Implementation on a NUMA Architecture
UPC is an explicit parallel extension of ANSI C, which has been gaining rising attention from vendors and users. In this work, we consider the low-level monitoring and experimenta...
François Cantonnet, Yiyi Yao, Smita Annared...
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
13 years 12 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...