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» Evaluating Hardware Compilation Techniques
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MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
14 years 2 days ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
DAC
1997
ACM
13 years 12 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
VEE
2012
ACM
255views Virtualization» more  VEE 2012»
12 years 3 months ago
Adding dynamically-typed language support to a statically-typed language compiler: performance evaluation, analysis, and tradeof
Applications written in dynamically typed scripting languages are increasingly popular for Web software development. Even on the server side, programmers are using dynamically typ...
Kazuaki Ishizaki, Takeshi Ogasawara, José G...
CF
2007
ACM
13 years 11 months ago
Fast compiler optimisation evaluation using code-feature based performance prediction
Performance tuning is an important and time consuming task which may have to be repeated for each new application and platform. Although iterative optimisation can automate this p...
Christophe Dubach, John Cavazos, Björn Franke...
CASES
2000
ACM
13 years 11 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung