1304 search results - page 24 / 261 » Evaluating Hardware Compilation Techniques |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floatinggate transistor conce...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
ACL
2004
13 years 9 months ago
2004
This paper describes and evaluates MOP, an IE system for automatic extraction of metalinguistic information from technical and scientific documents. We claim that such a system ca...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper addresses the problem of speeding up functional (delayindependent)logic simulation for synchronousdigital systems. The problem needs very little new motivation – cycl...
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...