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» Evaluating Hardware Compilation Techniques
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SPAA
2009
ACM
14 years 8 months ago
A lightweight in-place implementation for software thread-level speculation
Thread-level speculation (TLS) is a technique that allows parts of a sequential program to be executed in parallel. TLS ensures the parallel program's behaviour remains true ...
Cosmin E. Oancea, Alan Mycroft, Tim Harris
MOBISYS
2008
ACM
14 years 7 months ago
Symphony: synchronous two-phase rate and power control in 802.11 wlans
Adaptive transmit power control in 802.11 Wireless LANs (WLANs) on a per-link basis helps increase network capacity and improves battery life of Wifi-enabled mobile devices. Howev...
Kishore Ramachandran, Ravi Kokku, Honghai Zhang, M...
PPOPP
2010
ACM
14 years 5 months ago
Is transactional programming actually easier?
Chip multi-processors (CMPs) have become ubiquitous, while tools that ease concurrent programming have not. The promise of increased performance for all applications through ever ...
Christopher J. Rossbach, Owen S. Hofmann, Emmett W...
ASPLOS
2010
ACM
14 years 2 months ago
Request behavior variations
A large number of user requests execute (often concurrently) within a server system. A single request may exhibit fluctuating hardware characteristics (such as instruction comple...
Kai Shen
ACSAC
2009
IEEE
14 years 2 months ago
MAVMM: Lightweight and Purpose Built VMM for Malware Analysis
—Malicious software is rampant on the Internet and costs billions of dollars each year. Safe and thorough analysis of malware is key to protecting vulnerable systems and cleaning...
Anh M. Nguyen, Nabil Schear, HeeDong Jung, Apeksha...