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» Evaluating Hardware Compilation Techniques
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IVCNZ
1998
13 years 10 months ago
A Survey and Evaluation of Mesh Reduction Techniques
: Large polygon meshes are a common entity in scienti c and engineering science. Polygon meshes can be used for simpli ed geometric operations such as collision detection and surfa...
Burkhard Wünsche
FCCM
2009
IEEE
172views VLSI» more  FCCM 2009»
14 years 3 months ago
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization
Abstract—Precision analysis and optimization is very important when transforming a floating-point algorithm into fixedpoint hardware implementations. The core analysis techniqu...
Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu,...
ACL
2001
13 years 10 months ago
Practical Issues in Compiling Typed Unification Grammars for Speech Recognition
Current alternatives for language modeling are statistical techniques based on large amounts of training data, and hand-crafted context-free or finite-state grammars that are diff...
John Dowding, Beth Ann Hockey, Jean Mark Gawron, C...
ICFP
2002
ACM
14 years 9 months ago
Compiling scheme to JVM bytecode: : a performance study
We have added a Java virtual machine (henceforth JVM) bytecode generator to the optimizing Scheme-to-C compiler Bigloo. We named this new compiler BiglooJVM. We have used this new...
Bernard P. Serpette, Manuel Serrano
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek