1304 search results - page 38 / 261 » Evaluating Hardware Compilation Techniques |
ITC
2000
IEEE
14 years 2 months ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
TOG
2002
13 years 9 months ago
2002
Rendering performance of consumer graphics hardware benefits from pre-processing geometric data into a form targeted to the underlying API and hardware. The various elements of ge...
IPPS
2000
IEEE
14 years 2 months ago
2000
IEEE
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
ACSAC
2005
IEEE
14 years 3 months ago
2005
IEEE
An Air Force evaluation of Multics, and Ken Thompson’s famous Turing award lecture “Reflections on Trusting Trust,” showed that compilers can be subverted to insert maliciou...
IPPS
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper presents reduction recognition and parallel code generationstrategies for distributed-memorymultiprocessors. We describe techniques to recognize a broad range of implic...