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» Evaluating Hardware Compilation Techniques
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LCPC
1999
Springer
14 years 2 months ago
Compiling for Speculative Architectures
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...
Seon Wook Kim, Rudolf Eigenmann
IPPS
2003
IEEE
14 years 3 months ago
A Compilation Framework for Distributed Memory Parallelization of Data Mining Algorithms
With the availability of large datasets in a variety of scientific and commercial domains, data mining has emerged as an important area within the last decade. Data mining techni...
Xiaogang Li, Ruoming Jin, Gagan Agrawal
DAC
2005
ACM
14 years 15 hour ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
ASPLOS
2010
ACM
14 years 4 months ago
CoreDet: a compiler and runtime system for deterministic multithreaded execution
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
Tom Bergan, Owen Anderson, Joseph Devietti, Luis C...
ISCA
1996
IEEE
103views Hardware» more  ISCA 1996»
14 years 2 months ago
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
Basem A. Nayfeh, Lance Hammond, Kunle Olukotun