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» Evaluating Hardware Compilation Techniques
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CGO
2010
IEEE
14 years 2 months ago
Efficient compilation of fine-grained SPMD-threaded programs for multicore CPUs
In this paper we describe techniques for compiling finegrained SPMD-threaded programs, expressed in programming models such as OpenCL or CUDA, to multicore execution platforms. Pr...
John A. Stratton, Vinod Grover, Jaydeep Marathe, B...
ESOP
2000
Springer
14 years 1 months ago
A Calculus for Link-Time Compilation
We present a module calculus for studying a simple model of link-time compilation. The calculus is stratified into a term calculus, a core module calculus, and a linking calculus. ...
Elena Machkasova, Franklyn A. Turbak
SC
2000
ACM
14 years 2 months ago
Using Hardware Performance Monitors to Isolate Memory Bottlenecks
In this paper, we present and evaluate two techniques that use different styles of hardware support to provide data structure specific processor cache information. In one approach...
Bryan R. Buck, Jeffrey K. Hollingsworth
FPGA
2008
ACM
161views FPGA» more  FPGA 2008»
13 years 11 months ago
Implementing high-speed string matching hardware for network intrusion detection systems
This paper presents high-throughput techniques for implementing FSM based string matching hardware on FPGAs. By taking advantage of the fact that string matching operations for di...
Atul Mahajan, Benfano Soewito, Sai K. Parsi, Ning ...
ISLPED
2004
ACM
119views Hardware» more  ISLPED 2004»
14 years 3 months ago
Application-level prediction of battery dissipation
Mobile, battery-powered devices such as personal digital assistants and web-enabled mobile phones have successfully emerged as new access points to the world’s digital infrastru...
Chandra Krintz, Ye Wen, Richard Wolski