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» Evaluating Hardware Compilation Techniques
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IEEEPACT
2008
IEEE
14 years 4 months ago
Redundancy elimination revisited
This work proposes and evaluates improvements to previously known algorithms for redundancy elimination. Enhanced Scalar Replacement combines two classic techniques, scalar replac...
Keith D. Cooper, Jason Eckhardt, Ken Kennedy
EMSOFT
2007
Springer
14 years 4 months ago
The revenge of the overlay: automatic compaction of OS kernel code via on-demand code loading
There is increasing interest in using general-purpose operating systems, such as Linux, on embedded platforms. It is especially important in embedded systems to use memory effici...
Haifeng He, Saumya K. Debray, Gregory R. Andrews
DSD
2010
IEEE
190views Hardware» more  DSD 2010»
13 years 10 months ago
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
I. Sajid, Sotirios G. Ziavras, M. M. Ahmed
CSMR
2004
IEEE
14 years 1 months ago
Rewrite Systems for Symbolic Evaluation of C-like Preprocessing
Automatic analysis of programs with preprocessing directives and conditional compilation is challenging. The difficulties range from parsing to program understanding. Symbolic eva...
Mario Latendresse
ACMMSP
2006
ACM
278views Hardware» more  ACMMSP 2006»
14 years 4 months ago
Atomicity via source-to-source translation
We present an implementation and evaluation of atomicity (also known as software transactions) for a dialect of Java. Our implementation is fundamentally different from prior work...
Benjamin Hindman, Dan Grossman