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» Evaluating Hardware Compilation Techniques
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FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 11 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana
CF
2004
ACM
14 years 3 months ago
Combining compiler and runtime IPC predictions to reduce energy in next generation architectures
Next generation architectures will require innovative solutions to reduce energy consumption. One of the trends we expect is more extensive utilization of compiler information dir...
Saurabh Chheda, Osman S. Unsal, Israel Koren, C. M...
ICCD
2005
IEEE
224views Hardware» more  ICCD 2005»
14 years 7 months ago
Algorithmic and Architectural Design Methodology for Particle Filters in Hardware
In this paper we present algorithmic and architectural methodology for building Particle Filters in hardware. Particle filtering is a new paradigm for filtering in presence of n...
Aswin C. Sankaranarayanan, Rama Chellappa, Ankur S...
PPOPP
2009
ACM
14 years 10 months ago
Solving dense linear systems on platforms with multiple hardware accelerators
In a previous paper we show how the FLAME methods and tools provide a solution to compute dense dense linear algebra operations on a multi-GPU platform with reasonable performance...
Enrique S. Quintana-Ortí, Francisco D. Igua...
RT
1998
Springer
14 years 2 months ago
Global Ray-Bundle Tracing with Hardware Acceleration
The paper presents a single-pass, view-dependent method to solve the general rendering equation, using a combined finite element and random walk approach. Applying finite element t...
László Szirmay-Kalos, Werner Purgath...