1304 search results - page 70 / 261 » Evaluating Hardware Compilation Techniques |
135
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FCCM
2003
IEEE
15 years 9 months ago
2003
IEEE
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
141
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MEMOCODE
2003
IEEE
15 years 9 months ago
2003
IEEE
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
163
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HPCA
1998
IEEE
15 years 8 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
133
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ICALP
2000
Springer
15 years 8 months ago
2000
Springer
Abstract. We describe SAFL, a call-by-value first-order functional language which is syntactically restricted so that storage may be statically allocated to fixed locations. Evalua...
116
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ISLPED
1999
ACM
15 years 8 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...