Sciweavers

1304 search results - page 73 / 261
» Evaluating Hardware Compilation Techniques
Sort
View
VEE
2006
ACM
178views Virtualization» more  VEE 2006»
15 years 10 months ago
Impact of virtual execution environments on processor energy consumption and hardware adaptation
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
Shiwen Hu, Lizy Kurian John
EGH
2005
Springer
15 years 10 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
15 years 10 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
15 years 11 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 10 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...