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» Evaluating Hardware Compilation Techniques
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SIGMETRICS
2004
ACM
141views Hardware» more  SIGMETRICS 2004»
15 years 10 months ago
CapProbe: a simple and accurate capacity estimation technique for wired and wireless environments
The problem of estimating the capacity of an Internet path is one of fundamental importance. Due to the multitude of potential applications, a large number of solutions have been ...
Rohit Kapoor, Ling-Jyh Chen, Alok Nandan, Mario Ge...
PLDI
1994
ACM
15 years 8 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
DATE
2003
IEEE
122views Hardware» more  DATE 2003»
15 years 9 months ago
Synthesis of Complex Control Structures from Behavioral SystemC Models
In this paper we present the results of a set of experiments we conducted in order to evaluate the viability of the behavioral synthesis, relying on the tools available at the mom...
Francesco Bruschi, Fabrizio Ferrandi
ICS
1999
Tsinghua U.
15 years 8 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...
ISPASS
2009
IEEE
15 years 11 months ago
Machine learning based online performance prediction for runtime parallelization and task scheduling
—With the emerging many-core paradigm, parallel programming must extend beyond its traditional realm of scientific applications. Converting existing sequential applications as w...
Jiangtian Li, Xiaosong Ma, Karan Singh, Martin Sch...