127 search results - page 16 / 26 » Evaluating Hardware Support for Reference Counting Using Sof... |
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
SBACPAD
2004
IEEE
13 years 8 months ago
2004
IEEE
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
We present HybridOS, a set of operating system extensions for supporting fine-grained reconfigurable accelerators integrated with general-purpose computing platforms. HybridOS spe...